序：
分频源程序：libraryIEEEuseIEEESTD_LOGIC_1164ALLuseIEEESTD_LOGIC_ARITHALLuseIEEESTD_LOGIC_UNSIGNEDALLe
tityfe
pi
2isportclk_750ki
std_logic系统时钟clk_13bufferstd_logic13分频clk_15bufferstd_logic15分频clk_1bufferstd_logic1分频e
dfe
pi
2architecturert1offe
pi
2issig
alq_13i
tegerra
ge0to28845定义中间信号量sig
alq_15i
tegerra
ge0to24999sig
alq_1i
tegerra
ge0to374999begi
processclk_750kbegi
ifclk_750keve
ta
dclk_750k1the
ifq_1328845the
q_130clk_13
otclk_13elseq_13q_131e
dif得13hz频率信号ifq_1524999the
q_150clk_15
otclk_15elseq_15q_151e
dif得15hz频率信号ifq_1374999the
q_10clk_1
otclk_15elseq_1q_11e
dif得1hz频率信号e
dife
dprocesse
drt1计量源程序：libraryIEEEuseIEEESTD_LOGIC_1164ALLuseIEEESTD_LOGIC_ARITHALLuseIEEESTD_LOGIC_UNSIGNEDALLe
tityjilia
gis
fportstarti
std_logic计费开始信号fi
i
std_logic里程脉冲信号stopi
std_logic行驶中，中途等待信号clk1i
std_logic驱动脉冲e
1e
0bufferstd_logic计费单价使能信号k1k0bufferstd_logic_vector3dow
to0行驶公里计数m1m0bufferstd_logic_vector3dow
to0等待时间计数e
djilia
garchitecturert2ofjilia
gissig
alwi
tegerra
ge0to59计时范围059begi
processclk1begi
ifclk1eve
ta
dclk11the
ifstart0the
w0e
10e
00m1