DPROCESSP500HZPROCESSq1KHzq1KHz作为输入信号，分出q500HzVARIABLEcoutINTEGER0BEGINIFq1KHzEVENTANDq1KHz1THENcoutcout1IFcout1THENq500Hz0二分频ELSIFcout2THENcout0q500Hz1ENDIFENDIFENDPROCESSP2HZPROCESSq500HzVARIABLEcoutINTEGER0BEGINIFq500HzEVENTANDq500Hz1THENcoutcout1IFcout125THENq2Hz0ELSIFcout250THENq2Hz1ELSEcout0ENDIFENDIFENDPROCESSP1HZPROCESSq2HzVARIABLEcoutINTEGER0BEGINIFq2HzEVENTANDq2Hz1THENcoutcout1IFcout1THENq1Hz0ELSIFcout2THENcout0q1Hz1ENDIFENDIFENDPROCESSENDbhv（3）模块图
4
f42控制器模块
（1）模块说明：输入端口e
set，k，set键来控制6个状态，这六个状态分别是显示计时时间状态，调计时的时、分、秒状态，调闹铃的时、分的状态，reset键是复位键，用来回到显示计时时间的状态。（2）源程序：libraryieeeuseieeestd_logic_1164alle
tityco
tlisportclke
setksetreseti
std_logiccthctmctscbhcbmflashhflashmflashssel_showoutstd_logice
dco
tlarchitecturertlofco
tlistypestatsiss0s1s2s3s4s5定义6个状态sig
alcurre
t_state
ext_statestatss0begi
processclkresetbegi
ifreset1the
curre
t_states0elsifclkeve
ta
dclk1the
ifreset0the
curre
t_state
ext_statee
dife
dife
dprocessprocesscurre
t_statee
setksetbegi
casecurre
t_stateiswhe
s0cth0ctm0cts0cbh0cbm0flashh0flashm0flashs0sel_show0ife
set1a
dk1the
若e
set和k为“1”，
ext_states1由s0态转到s1态else
ext_states0e
difwhe
s1ctm0cts0cbh0cbm0flashh1flashm0flashs0sel_show0ifset1the
cth1若set为“1”，cth输出“1”elsecth0进入调小时状态。e
difife
set1a
dk0the
若e
est为“1”k为“0”，
ext_states2由s1态转到s2态
5
fwhe

whe

whe

whe

else
ext_states1e
difs2cth0cts0cbh0cbm0flashh0flashm1flashs0sel_show0ifset1the
ctm1elsectm0e
difife
set1a
dk1the
ext_states3else
ext_states2e
difs3cth0ctm0cbh0cbm0flashh0flashm0flashs1sel_show0ifset1the
cts1elsects0e
difife
set1a
dk0the
ext_states4else
ext_states3e
difs4cth0ctm0cts0cbm0flashh1flashm0flashs0sel_show1ifset1the
cbh1elsecbh0e
difife
set1a
dk1the
ext_states5else
ext_states4e
difs5cth0ctm0cts0cbh0flashh0flashm1flashs0sel_show1ifset1the
cbm1elsecbm0e
difife
set1a
dk0the
ext_states0else
ext_r