states5e
dif
e
dcasee
dprocesse
drtl（3）仿真波形图
6
f（4）模块图
43二选一模块
（1）源程序：ENTITYmux21aISPORTabsINBITyOUTBITENDENTITYmux21aARCHITECTUREo
eOFmux21aISBEGINPROCESSabsBEGINIFs0THENyaELSE若s0y输出a反之输出b。ybENDIFENDPROCESSENDARCHITECTUREo
e（2）仿真波形图：
7
f（3）模块图
44计时模块441秒计时模块
（1）源程序libraryieeeuseieeestd_logic_1164alluseieeestd_logic_u
sig
edalluseieeestd_logic_arithe
tityc
ts60isportsld0bufferstd_logic_vector3dow
to0小时个位sld1bufferstd_logic_vector7dow
to4小时十位cooutstd_logicresti
std_logicclki
std_logice
dc
ts60architecturertlofc
ts60isbegi
processclkrestbegi
ifrest1the
sld1