Copyrightc199219931994ExemplarLogicI
cAllrightsreservedThisdesig
impleme
tsaUARTVersio
11Origi
alCreatio
Versio
12Modifiedtostd_logictypesVersio
21Exte
dedresettobemoreeffectiveI
troducedOTHERSclausedow
loadfromwwwpldcomc
wwwfpgacomc

LIBRARYieeeuseieeestd_logic_1164alluseieeestd_logic_arithalluseieeestd_logic_u
sig
edall
ENTITYuartISPORTclkx16INstd_logicI
putclock16xbitclockreadINstd_logicReceiveddatareadstrobewriteINstd_logicTra
smitdatawritestroberxINstd_logicReceivedatali
eresetINstd_logiccleardepe
de
ciestxOUTstd_logicTra
smitdatali
erxrdyOUTstd_logicReceiveddatareadytobereadtxrdyOUTstd_logicTra
smitterreadyfor
extbyteparityerrOUTstd_logicReceiverparityerrorframi
gerrOUTstd_logicReceiverframi
gerroroverru
OUTstd_logicReceiveroverru
errordataINOUTstd_logic_vector0TO7Bidirectio
aldatabusENDuartARCHITECTUREexemplarOFuartIS
fTra
smitdataholdi
gregisterSIGNALtxholdstd_logic_vector0TO7Tra
smitshiftregisterbitsSIGNALtxregstd_logic_vector0TO7SIGNALtxtag2std_logictagbitsfordetecti
gSIGNALtxtag1std_logicemptyshiftregSIGNALtxparitystd_logicParityge
eratio
registerTra
smitclocka
dco
trolsig
alsSIGNALtxclkstd_logicTra
smitclock116thofclkx16SIGNALtxdo
estd_logic1whe
shifti
gofbyteisdo
eSIGNALparitycyclestd_logic1o
exttolastshiftcycleSIGNALtxdatardystd_logic1whe
dataisreadyi
txholdReceiveshiftregisterbitsSIGNALrxholdstd_logic_vector0TO7HoldsreceiveddataforreadSIGNALrxregstd_logic_vector0TO7ReceivedatashiftregisterSIGNALrxparitystd_logicParitybitofreceiveddataSIGNALparityge
std_logicGe
eratedparityofreceiveddataSIGNALrxstopstd_logicStopbitofreceiveddataReceiveclocka
dSIGNALrxclkSIGNALrxidleSIGNALrxdatardyreadBEGINmake_txclkPROCESSresetclkx16VARIABLEc
tstd_logic_vector2DOWNTO0BEGINToggletxclkevery8cou
tswhichdividestheclockby16IFreset1THENtxclk0c
tOTHERS0co
trolsig
alsstd_logicReceivedatashiftclockstd_logic1whe
receiverisidli
gstd_logic1whe
dataisreadytobe
fELSIFclkx16eve
tANDclkx161THENIFc
t