键盘PS2实验报告基础实验Top模块moduletopF50Mps2_clkps2_datarstsegweii
putF50Mi
putps2_clki
putps2_datai
putrstoutput60segoutput30weikeybkeyb_uF50MF50Mps2_clkps2_clkps2_dataps2_datarstrstsegsegweiweie
dmoduleKey模块modulekeybF50Mps2_clkps2_datarstsegweii
putF50Mi
putps2_clki
putps2_datai
putrstoutput30weioutput60seg
reg60segreg50
reg70doutwirebrega1rega2采ps2_clk的下降沿alwaysposedgeF50Morposedgerstbegi
ifrstbegi
a11a21e
delse
fbegi
a2a1a1ps2_clke
de
dassig
ba1a2ps2_clk下降沿时b产生一个时钟周期的高电平alwaysposedgeborposedgerstbegi
ifrstbegi
0dout0e
delseif
32计数到32，计数满33次时则表示传送数据完毕，可以全部清零begi
0dout0e
delsebegi
case
接收第2到第9个时刻的数据，不需要起始位6d1begi
dout0ps2_data
1e
d6d2begi
dout1ps2_data
1e
d6d3begi
dout2ps2_data
1e
d6d4begi
dout3ps2_data
1e
d6d5begi
dout4ps2_data
1e
d6d6begi
dout5ps2_data
1e
d6d7begi
dout6ps2_data
1e
d6d8begi
dout7ps2_data
1e
ddefault
1e
dcasee
de
dalwaysposedgeF50Morposedgerstbegi
ifrstbegi
seg7b0000000e
delseif
32接收完毕则可以转换成LED灯输出begi

fcasedout8h45seg7b000_00018h16seg7b100_11118h1Eseg7b001_00108h26seg7b000_01108h25seg7b100_11008h2Eseg7b010_01008h36seg7b010_00008h3Dseg7b000_11118h3Eseg7b000_00008h46seg7b000_0100defaultseg7b011_0000e
dcasee
de
dassig
wei4b0111e
dmodule约束条件NET