数字时钟模块（基于FPGA，Altera）r
moduleshuzishizho
gclksegdigr
i
putclkr
output70segdigr
reg70segdigr
reg20cou
tr
reg230dispr
reg250cou
t1r
reg310cou
t2r
regclk_outr
regclk_out1r
r
时钟部分r
r
数码管选择时钟r
alwaysposedgeclktr
begi
r
ifcou
t148000r
cou
t10r
elser
cou
t1cou
t126b1r
ifcou
t124000r
clk_outclk_outr
elseifcou
t148000r
clk_outclk_outr
e
dr
r
计数时钟r
alwaysposedgeclktr
begi
r
ifcou
t248000000r
cou
t20r
elser
cou
t2cou
t21r
ifcou
t224000000r
clk_out1clk_out1r
elseifcou
t248000000r
clk_out1clk_out1r
e
dr
r
数据处理部分r
计数部分r
alwaysposedgeclk_outr
begi
r
ifcou
t7r
cou
t0r
elser
cou
tcou
t3b1r
e
dr
r
alwaysposedgeclk_out1r
begi
r
ifdisp309begi
秒个位9时r
r
ifdisp745begi
秒十位5时r
disp744b0disp304b0r
ifdisp1189begi
分个位9时r
r
ifdisp15125begi
分十位5时r
disp15124b0disp1184b0r
ifdisp19163begi
时个位3时r
r
ifdisp23202时十位2时r
disp23200disp19164b0清0r
elsebegi
r
disp2320disp23204b1disp19164b0e
d时十位不2时，自加1，时个位清0r
e
dr
elsebegi
r
disp1916disp19164b1disp15124b0e
d时个位不3时：自加1，分十位清0r
e
dr
elsebegi
r
disp1512disp15124b1disp1184b0e
d分十位不5时：自加1，分个位清0r
e
dr
elsebegi
r
disp118disp1184b1disp744b0e
d分个位不9时：自加1，秒十位清0r
e
dr
elsebegi
r
disp74disp744b1disp304b0e
d秒十位不5时：自加1，秒个位清0r
e
dr
elser
disp30disp304b1秒个位不9时：自加1r
e
dr
r
数据显示部分r
alwaysposedgeclk_outr
begi
r
ifcou
t7r
begi
r
r
casedisp2320r
4b0000begi
dig8b01111111seg8hc0e
dr
4b0001begi
dig8b01111111seg8hf9e
d选择数码管8显示小时十位：02r
4b0010begi
dig8b01111111seg8ha4e
dr
r
e
dcaser
e
dr
elseifcou
t6r
begi
r
r
casedisp1916r
4b0000begi
dig8b10111111seg8hc0e
dr
4b0001begi
dig8b10111111seg8hf9e
d选择数码管7显示小时个位：03r
4b0010begi
dig8b10111111seg8ha4e
dr
4b0011begi
dig8b10111r