te1state1_
ege
d
elseifswitch01begi
state1state1_spe_01e
d
state1_spe_01ifswitch00
begi
state1state1_spe_02cou
t139
e
delsestate1state1_spe_01
state1_spe_02ifcou
t10begi
cou
t1cou
t11e
d
felsestate1state1_
eg
state1_
egbegi
light0b0state1IDLE1cou
ter13b0e
d
state1_posbegi
light01state1state1_mai
e
d
defaultstate1IDLE1e
dcase
Theseco
dalwaysblockTodealwithlight2switch2alwaysposedgeclk10
ifrstbegi
state2IDLE2cou
t28b0cou
ter23b0e
d
felseifswitch11b1cou
ter25cou
ter2cou
ter21
elsecasestate2
IDLE2ifswitch1b1
begi
state2state2_poscou
t279
e
delse
begi
state2IDLE2light1b0
e
d
state2_mai
ifcou
t20
begi
cou
t2cou
t21
e
delse
ifswitch10begi
state2state2_
ege
d
elseifswitch11begi
state2state2_spe_01
fe
d
state2_spe_01ifswitch10
begi
state2state2_spe_02cou
t239
e
delsestate2state2_spe_01
state2_spe_02ifcou
t20begi
cou
t2cou
t21e
delsestate2state2_
eg
state2_
egbegi
light1b0state2IDLE2cou
ter23b0e
d
state2_posbegi
flight1b1state2state2_mai
e
ddefaultstate2IDLE2e
dcase
ThethirdalwaysblockTodealwithlight3switch3alwaysposedgeclk10
ifrstbegi
state3IDLE3cou
t38b0cou
ter33b0e
d
elseifswitch21b1cou
ter35cou
ter3cou
ter31
elsecasestate3
IDLE3ifswitch2b1
begi
state3state3_poscou
t379
e
delse
begi
state3IDLE3light20
fe
d
state3_mai
ifcou
t30
begi
cou
t3cou
t31
e
delse
ifswitch20begi
state2state3_
ege
d
elseifswitch21begi
state3state3_spe_01e
d
state3_spe_01ifswitch20
begi
state3state3_spe_02cou
t339
e
delsestate3state3_spe_01
state3_spe_02
fifcou
t30begi
cou
t3cou
t31e
d
elsestate3state3_
eg
state3_
egbegi
light1b0state3IDLE3cou
ter33b0e
dstate3_posbegi
light2b1state3state3_mai
e
ddefaultstate3IDLE3e
dcase
e
dmodule五.综合仿真结果
f实验思考与总结
Verilog是硬件描述语言的一种,用于数字电子系统设计,它允许我们进行各种级别的逻辑设计,进行数字逻辑系统的仿真验证、时序分析、逻辑综合,是目前应用最广泛的一种硬件描述语言。Verilog有许多优点,首先,由于verilog的标准化,可以很容易的把完成的设计移植到不同厂家的不同芯片上去,并在不同规模的应用时可以比较容易的做修改。这不仅是因为用verilog所完成的设
f计,其信号位数是很容易改变的,可以很容易的对它进行修改,来适应不同规模的应用在仿真验证时,仿真测试矢量还可以用同一种描述语言来完成,而且还因为采用VerilogHDL综合器生成的数字逻辑是一种标准的电子设计互换格式文件,独r